1. Field of the Invention
The present invention relates to a thin film transistor liquid crystal display (LCD), and more particularly, to a source driver circuit for use in a thin film transistor LCD, which is capable of reducing the slew rate of color data.
2. Description of the Related Art
In general, a liquid crystal display (LCD) includes a gate driver that actuates gate lines of a panel, and a source driver that actuates source lines of the panel. The LCD displays an image, or screen, on the panel by applying high voltage to the panel with the gate driver to cause an electric current to flow through the panel, and then applying a gradient voltage, which is a signal output from a source driver, and indicates the color of an image, to each source line with the source driver.
More specifically, the source driver receives color data of 6 bits per pixel, which is to be displayed on the panel, from a processor. Then, color data corresponding to a pixel of a gate line of the panel is input to and latched in the source driver. After the color data for each gate line of the panel is latched, the latched color data is multiplexed into color data for each pixel and then voltages for displaying color are simultaneously applied to the lines of the panel. At this time, the gate driver applies high voltage to only one gate line and turns on a transistor so as to store color data, which has been applied to the source line, in a corresponding gate line. As a result, each of the voltages for displaying colors are stored, thereby displaying a color for each pixel.
FIG. 1 is a block diagram of a source driver circuit 100 of a conventional thin film transistor LCD, and FIG. 2 is a timing diagram of the operation of the source driver circuit 100 of FIG. 1.
Referring to FIG. 1, the conventional source driver circuit 100 includes a shift register 110, a first data latch 120, a second data latch 130, a decoder 140 and an output buffer 150. The shift register 110 receives a main clock signal MCLK and applies it to the first data latch 120. In response to the main clock signal MCLK, color data DATA is input to, and latched by, the first data latch 120. The second latch 130 receives the color data DATA from the first data latch 120, and outputs it in response to a first clock signal CLK1. The decoder 140 receives the color data DATA output from the second latch 130 and causes the color data DATA to maintain a normal voltage level in response to a voltage control signal VGMA. The output buffer 150 receives the color data DATA having a normal voltage level, inverts the polarity of color data YDATA in response to a polarity inversion signal POL, which indicates whether the voltage level of the color DATA is higher or lower than a predetermined reference voltage, and outputs the color data YDATA to a panel 160.
Here, the slew rate of the color data YDATA, which is output from the buffer 150 in the source driver circuit 100, is one of the primary factors that determine the quality of an image. In particular, since a panel of an ultra extended graphics array (UXGA) grade has a horizontal synchronization period of 13–15 μs at maximum, it is difficult to produce an image of good quality in the event that the slew rate of the color data YDATA is more than 3 μs.
The slew rate of the color data YDATA output from the output buffer 150 is limited by the large load of the panel 160. The color data YDATA output from the output buffer 150 cannot be in the square wave form because of the resistance or capacitance of the panel external to the source driver circuit 100.
Referring to FIG. 2, the color data YDATA output from the output buffer 150 is output in response to a first clock signal CLK1. Here, it is noted that the polarity of the color data YDATA changes with respect to a reference voltage VCOM whenever the phase of a polarity inversion signal POL changes.
The color data YDATA is output in response to the first clock signal CLK1. The first clock signal CLK1 is a signal applied to the second data latch 130. Thus, the slew rate of the color data YDATA contains information with respect to the time required for the second data latch 130 to move data to the output buffer 150. FIG. 2 reveals that if the color data YDATA has a long slew rate, the output curve of the color data YDATA changes to a certain degree. Accordingly, an increase in the slew rate results in an increase in power consumption in the source driver circuit. In addition, the characteristics of the panel 160 of FIG. 1, having high load and definition, can become unstable.